第一階段;乘法機之行為模式設計考試

2007/04/29

第一階段 ASM圖

程式碼如下

`define NUM_STATE_BITS 3
`define IDLE 3'b000
`define INIT 3'b001
`define COMPUTE1 3'b010
`define COMPUTE2 3'b011
`define INIT1 3'b100

module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;

initial
clk = 0;

always
#50 clk = ~clk;

always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;

endmodule

module slow_div_system(pb,ready,x,y,r3,sysclk);
input pb,x,y,sysclk;
output ready,r3;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2,r3;
reg [`NUM_STATE_BITS-1:0] present_state;

always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x;
ready = 1;
if (pb)
begin
@(posedge sysclk) enter_new_state(`INIT);
r2 <= @(posedge sysclk) 0;
@(posedge sysclk) enter_new_state(`INIT1);
r3 <= @(posedge sysclk) 0;
while (r2 < y)
begin
@(posedge sysclk) enter_new_state(`COMPUTE1);
r2 <= @(posedge sysclk) r2 + 1;
@(posedge sysclk) enter_new_state(`COMPUTE2);
r3 <= @(posedge sysclk) r3 + r1;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask

always @(posedge sysclk) #20
$display("%d r1=%d r2=%d pb=%b ready=%b", $time, r1,r2, pb, ready);
endmodule

module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 4;
y = 5;
#250;
@(posedge sysclk);

begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x*y === quotient)
$display("ok");
else
$display("error x=%d y=%d x*y=%d quotient=%d",x,y,x*y,quotient);
end
$stop;
endendmodule

測試4X5之結果圖

第二階段 除法機混合模式設計"模擬圖"

2007/4/2

第一階段"乘法機"Verilog 程式設計

2007/3/19
除法機 修改為 乘法機 完成圖

計算機設計

2007/3/12
今天上課初步認識課程中會用到的工具軟體SynaptiCAD,也將範例做了些試驗,因為之前都沒修過老師的課,對於軟體的使用並不了解,相信在使用幾次後就會熟練多了!!